The present invention relates to a method of forming a bottom source-drain for vertical field-effect transistors and the vertical field-effect transistors formed therefrom.
In a conventional field-effect transistor (FET), the source, the drain, and the gate electrodes are arranged on the same major surface of a semiconductor, where the gate voltage controls current flow in a direction parallel to the major surface of the semiconductor that extends between the source and drain. The performance of a conventional FET depends on the doping profile, the quality of the material proximate the surface (i.e., the active layer), and the geometry of the device.
In some applications, for example, where high power capability is desired, multiple conventional FET devices are connected in parallel with one another. Because all three of the source, the drain, and the gate electrodes of each respective conventional FET are located on the same surface, relatively complicated crossover metallization patterns are required to effect the parallel connections.
In order to overcome some of these drawbacks, vertical FETs were developed. In contrast to conventional FETs, in vertical FET devices, the source to drain current flows in a direction perpendicular to the major surface of the semiconductor. For example, if the substrate surface is made horizontal, then the vertical FET is typically a vertical pillar with the drain and source being the top and bottom portion of the pillar. One of the main advantages of the vertical FET is that the channel length is not defined by lithography, but rather by methods such as epitaxial growth or layer deposition, which can provide good thickness control even at nanometer dimensions.